Objectives

High-level technology goals

• Hybrid bonding for multi-chip(let) assembly: The project develops die stacking by direct bonding of the surface dielectrics and embedded metal pads into a common technology for multi-chip(let) assemblies with micro-electronics components as well as with power-electronic components. The latter may use Si, SiC, or GaN devices. The expected high mechanical stresses in the chips are characterized using new test chips and measurements and managed through optimized pad designs and bonding processes.
• Robust Packaging for Versatile Electronic Components and Systems: At component, module, and system levels, solders and adhesives are replaced by fatigue-free sintering on substrates and by encapsulations for high-temperature operation (Tj→220°C), significantly reducing the system cooling requirements. Innovative sintering processes enable >100 joints. Suitable organic substrate and mold materials result in affordable and robust electronic components and systems.
• Highly Efficient and Flexible Equipment for Packaging Production: Half of the project resources are dedicated to preventing the process results from getting stuck in the “valley of death”. Global market leaders Besi and Zeiss each improve major key performance indicators of their already world-class die‑to‑wafer hybrid bonders with nanometre‑scale alignment accuracy and throughput up to 3000 units per hour and the world’s first inline 3D X‑ray tomography tool for hybrid bonding, capable of minute‑scale wafer inspection with AI‑driven defect detection. Furthermore, Budatec introduces a breakthrough sintering tool with significantly improved mold capabilities. These tools close the loop between process development, quality control, and volume manufacturing.